1. Technical Field
The present invention relates in general to semiconductor design automation systems, more particularly to the simulation of integrated circuit designs of such systems, and more particularly to the accurate determination of net (wiring) performance for such integrated circuit designs.
2. Description of the Related Art
Development of a working integrated circuit chip is a process that involves creating a design specification, creating the logical design of the chip (typically in schematic form), validating the design, re-designing as necessary, fabricating the chip and testing the chip. Costs tend to be “end-loaded,” i.e., greater towards the end of the process than towards the beginning. The earlier in this process that a design error is detected, the earlier it can be corrected, saving a great deal of cost over a late-detected error. As a result, increasingly sophisticated steps are being taken to validate the design of a new chip, as early in the design process as possible.
Design validation requires thorough examination of the integrated circuit design and expected functional characteristics, taking into account a number of different factors, such as logical correctness of the design, timing factors (including net delay performance, effects of parasitic capacitances, etc.). Among these factors, net performance (specifically, net delay) is one of the most important. Many timing-related problems have been discovered in chips whose designs appear to be “logically” correct, at least on paper. This is because it is difficult for the designer to anticipate such delay contributors as wiring delays, i.e., net delays and the cumulative effects of distributed resistances and capacitances on the chips, especially from a post-layout point of view. The accuracy of delay determination affects not only the chip performance, but whether a chip meets its original design specification.
Virtually all integrated circuit designers today use semiconductor design automation systems which facilitate the capture, simulation, layout, and verification of integrated circuit designs. With the advance of semiconductor process technology, integrated circuits are becoming increasingly fast, and the once relatively small delays caused by interconnections, i.e., wiring, on a chip are becoming a more dominant factor in integrated circuit performance. As a result, the ability to accurately model and calculate wiring delays is becoming a crucial requirement for any semiconductor design automation system. These wiring delays, i.e., the time required for a critical threshold voltage at a receiving node to be crossed after the application of a driving signal at a driving node, are known as “net delays.”
One of the by-products of an integrated circuit design on a semiconductor design automation system is a “net-list” which contains a complete description of all of the devices, e.g., transistors, resistors, etc., required and how they are connected. The connections are described in the form of “nets” (short for “networks”) or descriptions of the point-to-point wiring connections between components. A single net may connect to many components. Any chip design will have a great number of nets. The net-list includes a list of net interconnections, thus the name “net-list”.
From any driving point to any receiving point on a net, there is an associated delay. This time is due to a complicated combination of parasitic capacitances, wiring resistances, wire lengths, etc. Some nets have multiple drivers, e.g., a number of open-drain or tri-state drivers, or loops, e.g., clock rings, making their (accurate) analysis particularly complicated. The delay for a net is determined by modeling the net and analyzing the delay according to the model. One of the most serious problems in delay calculation (determination) is that accurate models tend to complicate delay calculations, resulting in expensive delays in the design cycle while computation-intensive net delays are being calculated. As a result, most prior-art net delay calculation techniques compromise on the accuracy (faithfulness to reality) of the model of the net in order to decrease the amount of calculation time required. Unfortunately, in doing so most such techniques sacrifice enough accuracy that the results of delay calculation are only very rough approximations of actual chip performance. As a result, many chips, particularly those with complicated timing relationships between signals, have subtle timing-related problems when they are built. The designs of such chips must then be altered, re-simulated, etc., and a new chip must be fabricated. This process is extremely costly.
Despite it being more than fifty (50) years old, the Elmore delay metric is widely employed in conventional Physical design tools. The popularity of the Elmore delay model is not surprising considering that it is, firstly, a fairly accurate measure of the true delay at far-end nodes, i.e., nodes far from the driving source. Secondly, it is expressible as a closed-from expression involving only the resistors and capacitors of the circuit under evaluation. Thirdly, it is a provable upper bound on the true delay for all inputs and finally, it is additive, i.e., the delay from node A to node C of a path passing through node B is the sum of delays from nodes A to B and from nodes B to C. Additivity offers the advantage of decoupling optimization problems into sub-problems, allowing optimal algorithms, e.g., for buffer insertion and wiresizing. However, the only attribute (and arguably the most important) that the Elmore delay lacks is consistent accuracy at all nodes. The Elmore delay can be inaccurate by orders of magnitude, especially for near-end, i.e., nodes close to the driving source.
Consequently, several other delay metrics based on higher-order moments have been proposed, see e.g., A B. Kahng and S. Muddu, “Two-pole Analysis of Interconnection trees,” Proceeding IEEE Multi-Chip Module Conference, Santa Cruz, February 1995, pp. 105–110 and A. B. Kahng and S. Muddu, “A General Methodology for Responses and Delay Computations in VLSI Interconnects,” UCLA CS Dept. TR-940015, 1994. While these approaches are typically more accurate than Elmore and simpler than truly actuate methods, see e.g., L. T. Pillage and R. A. Rohrer, “Asymptotic Waveform Evaluation for Timing Analysis,” IEEE TCAD, 9(4), 352–366, 1990, some of the simplicity of the Elmore delay is lost. All of these metrics use multiple moments of the transfer function, which makes them non-additive.
Accordingly, what is needed in the art is an improved signal delay metric that mitigates the above-discussed limitations in the prior art.